A typical class-D output stage comprises two n-type power MOSFETs in a totempole configuration as shown in FIG. 1. The output node Vout is switched between the supply lines using pulse-width modulation (PWM). An LC-low-pass filter is usually inserted between the output node Vout and the load, which may be a loudspeaker for filtering out the high frequency content of a signal delivered by the amplifier. Inverters Mph/nh and Mpl/nl drive the gates of the power MOSFETs MH and ML. The dimensions of these inverters together with the parasitic capacitances Cgdl and Cgdh of the power MOSFETs determine the dynamic behavior of the class-D output stage. FIG. 2 shows some typical waveforms that occur during a falling transition at the output when no output current is flowing. Vgsl is the gate-source voltage of the lowside power MOSFET ML and Vgsh is the gate-source voltage of the highside power MOSFET MH. In this case the highside power MOSFET MH is switched off while the lowside power MOSFET ML is switched on. As can be seen three phases can be distinguished in the transition. In phase I the gate of the highside power MOSFET MH is discharged rapidly while the gate of the lowside power MOSFET ML is charged. In a properly dimensioned output stage the highside power MOSFET MH will be switched off before the lowside power MOSFET ML starts to conduct, i.e. before the gate-source voltage Vgsl reaches the threshold voltage VT. The output voltage Vout remains where it is during this phase. In phase II Vgsl crosses the threshold level and the lowside power MOSFET ML starts conducting, thus pulling down the output node Vout. This determines the typical stalling of Vgsl because during the transition all available charging current will be flowing into the gate-drain capacitance Cgdl of the lowside power MOSFET ML. The speed of the transition is governed by the size of Mpl and the gate-drain capacitance Cgdl. Finally, in phase III the transition of the output node Vout has ended and Vgsl rises again to its final value which is typically a few times the threshold voltage VT of the transistor. The waveforms that occur during a rising transition at the output are similar but the role of the highside and lowside power MOSFETs is interchanged. The speed of the transition can be controlled by the size of the driver transistors. However, the ratio of the driver transistors Mph/Mnl (or Mpl/Mnh) is fixed to guarantee reliable operation. In general the NMOS transistors in the driver need to be more powerful (low-ohmic) than the PMOS transistors in order to avoid cross conduction. As it is shown in M. Berkhout, “A Class-D Output Stage with Zero Dead Time”, ISSCC Dig. Tech. Papers, pp. 134-135, February 2003.
The situation changes significantly if a substantial current Iout flows from or towards the output stage. FIG. 3 depicts the waveforms when a large current flows from the amplifier. Now during phase I as soon as Vgsh starts to fall the output current Iout pulls down the output node Vout immediately entering phase II. This transition is so fast that the highside power MOSFET is not switched off completely but remains conducting during the transition. In this case the speed of the transition is actually governed by the size of driver transistor Mnh and gate-drain capacitance Cgdh. At the lowside Vgsl initially starts to rise but is then pushed down through Cgdl. Although there still is no cross conduction the output transitions tend to become much faster then in the case where no output current is flowing. After the transition has finished the gate of the lowside power MOSFET is charged to its final value during phase III.
FIG. 4 shows the waveforms when a large output current Iout flows towards the output stage. In phase I the gate of the highside power MOSFET MH is discharged causing the output current to flow through the back-gate diode of MH. At the same time the gate of the lowside power MOSFET ML is charged. Now as Vgsl reaches the threshold level the lowside power MOSFET ML starts to conduct but the output node Vout remains at the highside until the current through ML matches the output current Iout causing Vgsl to increase further. Now the most important problem occurs. When the output node Vout is pulled down the voltage across the (conducting) back-gate diode is reversed. This results in a reversal of the diode current due to a well-known effect called reverse recovery. In the lowside power MOSFET ML the reverse recovery current adds to the output current causing Vgsl to increase even further. The reverse recovery current tends to stop quite abruptly when the diode runs out of minority carriers. However at the lowside power MOSFET ML the gate-source voltage Vgsl has by now reached a value that corresponds to the output current plus the reverse recovery current which is almost equal to the output current Iout. As a result the output node Vout is initially pulled down very fast. Then feedback through the gate-drain capacitance Cgdl causes Vgsl to be pushed down causing a characteristic ‘overshoot’ in Vgsl. Also the gate of the highside power MOSFET MH is pulled up which can lead to additional peak current if the threshold voltage VT is exceeded. After this rapid start the transition is continued at a more moderate pace during phase II and in phase III the charging of the gate of lowside power MOSFET ML is finished. The occurrence of reverse recovery and especially the rapid decrease of the reverse recovery current is probably the most important source of EMI i.e. electromagnetic Interference, in class-D amplifiers.